Disk evaluation device

ABSTRACT

The invention has an object to provide a disk evaluation apparatus capable of performing a highly reliable disk evaluation even on a recording disk on which information is recorded in high density. Amplitude-limited read sample value sequence are obtained by limiting read sample value sequence to a predetermined amplitude limit value, the read sample value sequence obtained by sampling a read signal read out from the recording disk as timed to a clock having the same frequency as that of a channel clock. Where a gap between a maximum sample value and a minimum sample value of the amplitude-limited read sample value sequence is equivalent to a predetermined distance of high-frequency wavelength, the maximum sample value and the minimum sample value are increased thereby to obtain high-frequency enhanced read sample value sequence enhanced at the high region thereof. The high-frequency enhanced read sample value sequence are converted to an analog high-frequency enhanced read signal as timed to the clock having the same frequency as that of the channel clock. Only components having frequencies equal to or smaller than a predetermined cutoff frequency are extracted from the high-frequency enhanced read signal so as to obtain an evaluation read signal. The evaluation read signal is binarized based on a predetermined threshold value to obtain a binary signal, which is outputted as a disk evaluation value.

TECHNICAL FIELD

[0001] The present invention relates to a disk evaluation apparatus forperforming quality evaluation of recording disks.

BACKGROUND ART

[0002] Presently, the quality of a manufactured recording disk isevaluated based on jitter occurring on a signal read from the recordingdisk. However, as the recording density of information recorded on therecording disk increases, the read signal is not only decreased in theS/N ratio of high frequency components but also becomes more susceptibleto intersymbol interference. Therefore, a greater jitter than anintrinsic jitter is detected from the read signal acquired from therecording disk on which the information is recorded in high density.This results in a problem that the recording disk cannot be evaluatedcorrectly.

[0003] The invention is directed to a solution to such a problem. Anobject of the invention is to provide a disk evaluation apparatuscapable of performing a highly reliable disk evaluation even on therecording disk on which the information is recorded in high density.

DISCLOSURE OF THE INVENTION

[0004] According to the invention, a disk evaluation apparatus forevaluating a recording disk on which a modulation signal is recorded,the modulation signal obtained by performing a predetermined modulationprocessing on information data according to a channel clock, theapparatus includes: information reading means for acquiring a readsignal by reading out the modulation signal from the recording disk; anA/D converter for obtaining read sample value sequence by sampling theread signal as timed to a clock having the same frequency as that of thechannel clock; amplitude limiter means for obtaining amplitude-limitedread sample value sequence by limiting the individual sample values ofthe read sample value sequence to a predetermined amplitude limit valueor less; a high-frequency enhancement filter operative to increase amaximum sample value and a minimum sample value when a gap between themaximum sample value and the minimum sample value of theamplitude-limited read sample value sequence is equivalent to apredetermined distance of a high-frequency wavelength, thereby obtaininghigh-frequency enhanced read sample value sequence enhanced at the highregion thereof; a D/A converter for converting the high-frequencyenhanced read sample value sequence to an analog high-frequency enhancedread signal as timed to the clock having the same frequency as that ofthe channel clock; a lowpass filter operative to extract, from thehigh-frequency enhanced read signal, only components having frequenciesequal to or lower than a predetermined cutoff frequency, therebyobtaining an evaluation read signal; and a binarization circuitoperative to binarize the evaluation read signal based on apredetermined threshold value thereby obtaining a binary signal, theapparatus considering a jitter of the binary signal as a disk evaluationvalue.

BRIEF DESCRIPTION OF THE DRAWINGS

[0005]FIG. 1 is a diagram showing an arrangement of a disk evaluationapparatus according to the invention.

[0006]FIG. 2 is a diagram showing an internal arrangement of a limitequalizer 10.

[0007]FIG. 3 is a diagram showing one example of interpolated readsample value sequence RS_(P) and one example of amplitude-limitated readsample value sequence RS_(LIM).

[0008]FIG. 4 is a graph showing an output from the limit equalizer 10 incontrast to an output from an equalizer which does not perform highregion enhancement.

[0009]FIG. 5 is a diagram showing a frequency band of a high-frequencyenhanced read signal RD inputted to a post-lowpass filter 12.

[0010]FIG. 6 is a diagram showing an exemplary waveform of thehigh-frequency enhanced read signal RD inputted to the post-lowpassfilter 12 and an exemplary waveform of an evaluation read signal RRoutputted from the post-lowpass filter 12.

[0011]FIG. 7 is a graph showing a corresponding relation between thecutoff frequency of the post-lowpass filter 12 and the amount of jitterin a case where information data are RLL (1,7) modulated based on achannel clock at 66 MHz and recorded on a recording disk 3.

EMBODIMENT OF THE INVENTION

[0012] A preferred embodiment of the invention will be described below.

[0013]FIG. 1 is a diagram showing an arrangement of a disk evaluationapparatus according to the invention.

[0014] Referring to FIG. 1, a pickup 1 acquires a read signal R_(RF) byphotoelectrically converting a read light beam irradiated on andreflected from a recording surface of a recording disk 3 as anevaluation subject. The recording disk 3 is rotated by a spindle motor2. Previously recorded on the recording disk 3 is a modulation signalrepresentative of information data and obtained by an RLL (1,7)modulation processing performed according to a channel clock at 66 MHz,for example. A highpass filter 5 removes low region components from theaforesaid read signal R_(RF) so as to supply a read signal R_(HC) to apre-lowpass filter 6. In order to obviate aliasing during a samplingoperation performed by an A/D converter 7, the pre-lowpass filter 6removes, from the read signal R_(HC), high region components at ½ ormore of a sampling frequency so as to supply a read signal R_(LHC) tothe A/D converter 7. The A/D converter 7 acquires read sample valuesequence RS by sampling the read signal R_(LHC) according to a samplingclock SK supplied from a PLL (phase locked loop) circuit 8 and thensupplies the sample value sequence RS to a pre-equalizer 9. It is notedthat the sampling clock SK has the same frequency as the channel clockdescribed above. The pre-equalizer 9 obtains read sample value sequenceRS_(C) by removing, from such read sample value sequence RS, anintersymbol interference associated with transmission properties of aninformation reading system including the aforesaid pickup 1 andrecording disk 3. Then, the pre-equalizer supplies the resultant readsample value sequence RS_(C) to a limit equalizer 10. It is noted thatthe pre-equalizer 9 is a transversal filter having a tap coefficientsuch as [k, 1, 1, k].

[0015] The limit equalizer 10 performs a high-frequency enhancementprocessing on the aforesaid read sample value sequence RS_(C) withoutincreasing the intersymbol interference, thereby obtaininghigh-frequency enhanced read sample value sequence RS_(H). The limitequalizer supplies the resultant sample value sequence to the PLLcircuit 8 and a D/A converter 11

[0016]FIG. 2 is a diagram showing an internal arrangement of the limitequalizer 10.

[0017] As shown in FIG. 2, the limit equalizer 10 includes aninterpolation filter 41, an amplitude limiter circuit 42, ahigh-frequency enhancement filter 43, and an adder 44.

[0018] The interpolation filter 41 performs an interpolation operationon the aforesaid read sample value sequence RS_(C) thereby obtainingsample value sequence which would be acquired by sampling the readsignal read out from the recording disk 3 in an intermediate timing of aclock timing provided by the foresaid sampling clock SK. Theinterpolation filter 41 obtains interpolated read sample value sequenceRS_(P) by interpolating the resultant sample value sequence in theaforesaid read sample value sequence RS_(C) and then supplies theinterpolated read sample value sequence to the amplitude limiter circuit42.

[0019] The amplitude limiter circuit 42 limits the amplitude of theinterpolated read sample value sequence RS_(P) to predeterminedamplitude limit values T_(h) and −T_(h) thereby to. obtainamplitude-limited read sample value sequence RS_(LIM), which aresupplied to the high-frequency enhancement filter 43. In a case wherethe individual read sample values of the interpolated read sample valuesequence RS_(P) are in the range defined by the aforesaid amplitudelimit values of −T_(h) to T_(h), the amplitude limiter circuit 42directly supplies the interpolated read sample value sequence RS_(P), asthe aforesaid amplitude-limited read sample value sequence RS_(LIM), tothe high-frequency enhancement filter 43. In a case where the individualread sample values of the interpolated read. sample value sequenceRS_(P) are greater than the amplitude limit value T_(h), the amplitudelimiter circuit supplies a sequence of the amplitude limit value T_(h),as the amplitude-limited read sample value sequence RS_(LIM), to thehigh-frequency enhancement filter 43. On the other hand, in a case wherethe individual read sample values of the interpolated read sample valuesequence RS_(P) are smaller than the amplitude limit value −T_(h), theamplitude limiter circuit supplies a sequence of the amplitude limitvalue −T_(h), as the amplitude-limited read sample value sequenceRS_(LIM), to the high-frequency enhancement filter 43. In this process,the aforesaid amplitude limit values T_(h) and −T_(h) are each definedsuch that the individual samples are not subjected to the aforementionedamplitude limitation when a gap between the maximum sample and theminimum sample of the interpolated read sample value sequence RS_(P) isequal to a predetermined distance of a high region wavelength or equalto the shortest run length 2T in the RLL (1,7) modulation. That is, theinterpolated read sample value sequence RS_(P) corresponding to the runlength 2T are passed through the amplitude limiter circuit 42 as theyare, and then outputted as the amplitude-limited read sample valuesequence RS_(LIM).

[0020] The high-frequency enhancement filter 43 generates high-frequencyread sample value sequence by exclusively enhancing the level of thesample value sequence corresponding to the shortest run length 2T, whichare included in the aforesaid amplitude-limited read sample valuesequence RS_(LIM). The high-frequency enhancement filter supplies theresultant high-frequency read sample value sequence to the adder 44. Thehigh-frequency enhancement filter 43 is a transversal filter having atap coefficient of [−k, k, k, −k], for example. According to such anarrangement, the high-frequency enhancement filter 43 determines a valueat Time D₀ based on values at Times D_(−1.5), D_(−0.5), D_(0.5) andD_(1.5) included in the amplitude-limited read sample value sequenceRS_(LIM), as shown in FIGS. 3(a) and 3(b), for example. Thus, thehigh-frequency enhancement filter sequentially outputs the determinedvalue as a high-frequency read sample RS_(HIG), which is expressed as:RS_(HIG)=(−k)·Y_(−1.5)+k·Y_(−0.5)+(−k)·Y_(1.5)

[0021] Y_(−1.5): an amplitude-limited read sample at Time D_(−1.5) inRS_(LIM)

[0022] Y_(−0.5): an amplitude-limited read sample at Time D_(−0.5) inRS_(LIM)

[0023] Y_(0.5): an amplitude-limited read sample at Time D_(0.5) inRS_(LIM)

[0024] Y_(1.5): an amplitude-limited read sample at Time D_(1.5) inRS_(LIM)

[0025] As shown in FIG. 3(a), the amplitude-limited read samples atTimes D_(−1.5) and D_(−0.5) (or Times D_(0.5) and D_(1.5)) correspondingto the run length 2T are substantially equal to each other. As shown inFIG. 3(b), on the other hand, both the amplitude-limited read samples atTimes D_(−1.5) and D_(−0.5) (or Times D_(0.5) and D_(1.5)) correspondingto a run length 3T or 4T are at the amplitude limited value −T_(h) (orT_(h)) because of the operation of the amplitude limiter circuit 42.Accordingly, a high-frequency read sample obtained at a zero cross pointD₀ is maintained at a constant value even if the tap coefficient k ofthe high-frequency enhancement filter 43 is increased in order toprovide a strong high-frequency enhancement. Thus is obviated theintersymbol interference.

[0026] The adder 44 adds the high-frequency read sample value sequenceRS_(HIG) to the read sample value sequence RS_(C) supplied from theaforesaid pre-equalizer 9 and then, outputs the addition results as thehigh-frequency enhanced read sample value sequence RS_(H).

[0027] According to the aforementioned arrangement, the limit equalizer10 accomplishes the high region enhancement by increasing the maximumsample value and the minimum sample value of the aforesaid read samplevalue sequence RS_(C) when the gap between the maximum and minimumsample values of the read sample value sequence RS_(C) is equivalent tothe predetermined distance of the high region wavelength or to the runlength 2T in the RLL (1,7) modulation.

[0028]FIG. 4 is a graph showing spectrum (indicated by a solid line) ofthe high-frequency enhanced read sample value sequence RS_(H) obtainedthrough the high-frequency enhancement processing performed by theaforesaid limit equalizer 10, in contrast to spectrum (indicated by abroken line) of read sample value sequence obtained by an equalizerwhich does not perform such a high region enhancement. As shown in FIG.4, an output (indicated by the solid line) from the limit equalizer 10includes harmonic components which do not appear on an output (indicatedby the broken line) from the equalizer which does not perform the highregion enhancement.

[0029] The PLL circuit 8 generates a clock signal which is corrected forphase errors produced in the aforesaid high-frequency enhanced readsample value sequence RS_(H) and has the same frequency (66 MHz) as theaforesaid channel clock. The PLL circuit supplies the resultant clocksignal, as the aforesaid sampling clock SK, to the aforesaid A/Dconverter 7, the aforesaid D/A converter 11 and a jitter measurementcircuit 30. The D/A converter 11 converts the aforesaid high-frequencyenhanced read sample value sequence RS_(H) to an analog signal in atiming according to the sampling clock SK and supplies the resultantsignal, as a high-frequency enhanced read signal RD, to a post-lowpassfilter 12.

[0030] The post-lowpass filter 12 removes an aliasing component(described later) present in such a high-frequency enhanced read signalRD thereby extracting only a baseband component included in theaforesaid high-frequency enhanced read sample value sequence RS_(H).Then, the post-lowpass filter supplies the resultant signal, as anevaluation read signal RR, to a binarization circuit 13.

[0031] A specific operation of the post-lowpass filter 12 will bedescribed as below.

[0032]FIG. 5 is a diagram showing a frequency band of the high-frequencyenhanced read signal RD inputted to the post-lowpass filter 12.

[0033] The high-frequency enhanced read signal RD is obtained byconverting the aforesaid high-frequency enhanced read sample valuesequence RS_(H) to the analog signal as timed to the sampling clock SK.In the high-frequency enhanced read signal RD, therefore, the basebandcomponent of the high-frequency enhanced read sample value sequenceRS_(H) exists in a frequency band of ½ or less of the sampling frequencyfs (66 MHz) whereas the aliasing component thereof exists in a frequencyband of (½)·fs or more, as shown in FIG. 5. Hence, the post-lowpassfilter 12 takes an advantage of its cutoff properties as indicated by abroken line in FIG. 5 such as to remove the aliasing component of (½)·fsor more from the aforesaid high-frequency enhanced read sample valuesequence RS_(H). Thus, the post-lowpass filter 12 extracts only thebaseband component of the high-frequency enhanced read sample valuesequence RS_(H) from the high-frequency enhanced read signal RD andthen, outputs the resultant signal as the evaluation read signal RR.

[0034]FIG. 6 is a diagram showing an exemplary waveform of thehigh-frequency enhanced read signal RD inputted to the post-lowpassfilter 12 and an exemplary waveform of the evaluation read signal RRoutputted from the post-lowpass filter 12.

[0035] As shown in FIG. 6, the high-frequency enhanced read signal RD isobtained by the D/A converter 11 and hence, the waveform of the signalis shaped like steps due to the 0-order hold performance of theconverter. Therefore, the high-frequency enhanced read signal is notsuited for the jitter measurement. On this account, the post-lowpassfilter 12 is used to remove the aliasing component of the high-frequencyenhanced read sample value sequence RS_(H) which exists in thehigh-frequency enhanced read signal RD, thereby generating theevaluation read signal RR having a smooth waveform as shown in FIG. 6.

[0036]FIG. 7 is a graph showing a corresponding relation between thecutoff frequency of the post-lowpass filter 12 and the amount of jitterwhen the information data are RLL (1,7) modulated according to thechannel clock at 66 MHz and recorded on the recording disk 3.

[0037] In the example shown in FIG. 7, an objective lens (not shown)mounted in the pickup 1 has the following numerical aperture NA and awavelength λ:

NA=0.85

Wavelength λ=405 nm

[0038] In a case where the limit equalizer 10 is not used (indicated bya broken line), little jitter variations are observed if the cutofffrequency of the post-lowpass filter 12 is set to a value smaller than ½of the frequency of the channel clock, or 33 MHz. In the aforementionedcase where the limit equalizer 10 is used, however, the post-lowpassfilter 12, the cutoff frequency of which is set to a value greater than30 MHz, cannot fully attenuate the aliasing component of thehigh-frequency enhanced read sample value sequence RS_(H), as shown inFIG. 5. In consequence, the amount of jitter is increased as shown inFIG. 7. If the cutoff frequency of the post-lowpass filter 12 is set toa value smaller than 30 MHz, the harmonic component in thehigh-frequency enhanced read sample value sequence RS_(H), as indicatedby the solid line in FIG. 4, is attenuated so that the amount of jitteris increased as shown in FIG. 7.

[0039] In short, the amount of jitter is minimized where thepost-lowpass filter 12 has the cutoff frequency in the vicinity of 30MHz. In addition, if the post-lowpass filter 12 has the cutoff frequencyin the vicinity of 30 MHz, it is ensured that even if the post-lowpassfilter 12 is more or less varied in the cutoff frequency, the variationsof the jitter in conjunction with the cutoff frequency variations areinsignificant, as shown in FIG. 7.

[0040] Hence, it is preferred to set the cutoff frequency of thepost-lowpass filter 12 in the vicinity of 30 MHz when the aforesaidlimit equalizer 10 is employed for the evaluation of the recording disk3 on which the information data are recorded as RLL (1,7) modulatedaccording to the channel clock at 66 MHz. It is noted here that thecutoff frequency in the vicinity of 30 MHz is defined to includeallowable variations ±10% of the cutoff frequency from the viewpoint ofsuppressing the variations of the amount of jitter to 0.2% or less. Thatis, the cutoff frequency in the vicinity of 30 MHz is in the range of 27to 33 MHz. In a case where the disk is evaluated at a double speed(based on a channel clock at a frequency of 132 MHz), the cutofffrequency of the post-lowpass filter 12 may preferably be set in thevicinity of 60 MHz.

[0041] In short, the cutoff frequency fc of the post-lowpass filter 12may be decided such that fc/fclk may give a value of about 5/11,provided that the frequency of the channel clock is represented byfclk[MHz] and the cutoff frequency of the post-lowpass filter 12 isrepresented by fc[MHz].

[0042] In a case where the variations ±10% of the cutoff frequency aretaken into consideration, the cutoff frequency fc of the post-lowpassfilter 12 may be so decided as to satisfy:

9/22≦fc/fclk≦½.

[0043] The binarization circuit 13 generates a binary signal of apredetermined high voltage when the evaluation read signal RR suppliedfrom the aforesaid post-lowpass filter 12 is greater than apredetermined threshold value or a binary signal of a predetermined lowvoltage in a case where the evaluation read signal RR is smaller thanthe predetermined threshold value. Then, the binarization circuit 13supplies the resultant binary signal to the jitter measurement circuit30. The jitter measurement circuit 30 takes measurement on the variationof time difference between an edge timing of such a binary signal and aclock timing of a reference clock signal. That is, the jittermeasurement circuit 30 takes measurements on the amount of jitter andthen, outputs the measurement results as the disk evaluation value.

[0044] Thus, the jitter measurement circuit 30 takes measurement on theread signal which is obtained by performing the high region enhancementonly on the read sample value sequence equivalent to the shortest runlength by means of the limit equalizer 10 without causing theintersymbol interference, followed by removing the aliasing component bymeans of the post-lowpass filter 12, the aliasing component occurringduring the D/A conversion.

[0045] According to the disk evaluation apparatus of the invention, itis possible to evaluate the recording disk with high reliability even ifthe information is recorded on the recording disk in high density. Whenthe limit equalizer is applied to the disk evaluation apparatus, thelimit equalizer is allowed to fully present its effect to alleviatejitter by setting the cutoff frequency of the post-lowpass filter in amanner specified by the invention, although no consideration has beengiven to the cutoff frequency of the post-lowpass filter. Furthermore,even if the cutoff frequency of the post-lowpass filter is varied tosome degrees, the amount of jitter variations is insignificant.Consequently, the disk evaluation apparatus can provide a highlyreliable jitter evaluation which does not vary from one apparatus toanother.

1. A disk evaluation apparatus for evaluating a recording disk on whicha modulation signal is recorded, the modulation signal obtained byperforming a predetermined modulation processing on information dataaccording to a channel clock, the apparatus characterized by including:information reading means for acquiring a read signal by reading outsaid modulation signal from said recording disk; an A/D converter forobtaining read sample value sequence by sampling said read signal astimed to a clock having the same frequency as that of said channelclock; amplitude limiter means for obtaining amplitude-limited readsample value sequence by limiting the individual sample values of saidread sample value sequence to a predetermined amplitude limit value orless; a high-frequency enhancement filter operative to increase amaximum sample value and a minimum sample value when a gap between saidmaximum sample value and said minimum sample value of saidamplitude-limited read sample value sequence is equivalent to apredetermined distance of a high-frequency wavelength, thereby obtaininghigh-frequency enhanced read sample value sequence enhanced at the highregion thereof; a D/A converter for converting said high-frequencyenhanced read sample value sequence to an analog high-frequency enhancedread signal as timed to a clock having the same frequency as that ofsaid channel clock; a lowpass filter operative to extract, from saidhigh-frequency enhanced read signal, only components having frequenciesequal to or lower than a predetermined cutoff frequency, therebyobtaining an evaluation read signal; and a binarization circuitoperative to binarize said evaluation read signal based on apredetermined threshold value thereby obtaining a binary signal, theapparatus considering a jitter of said binary signal as a diskevaluation value.
 2. A disk evaluation apparatus according to claim 1,characterized in that the frequency of said channel clock is representedby fclk[MHz] and said cutoff frequency is represented by fc[MHz],fc/fclk gives a value of about 5/11.
 3. A disk evaluation apparatusaccording to claim 2, characterized in that said channel clock has afrequency of 66 MHz whereas said cutoff frequency is at 30 MHz.
 4. Adisk evaluation apparatus according to claim 1, characterized in thatthe frequency of said channel clock is represented by fclk[MHz] and saidcutoff frequency is represented by fc[MHz], the following expressionholds: 9/22≦fc/fclk≦1/2.
 5. A disk evaluation apparatus according toclaim 1, characterized in that said modulation processing is an RLL(1,7) modulation processing.
 6. A disk evaluation apparatus according toclaim 1, characterized in that said amplitude limit value is greaterthan said maximum sample value when the gap between the maximum samplevalue and the minimum sample value of said amplitude-limited read samplevalue sequence is equivalent to the predetermined distance of thehigh-frequency wavelength.
 7. A disk evaluation apparatus according toclaim 1, characterized in that said high-frequency enhancement filter isa transversal filter having a tap coefficient of [−k, k, k, −k].